A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder.
Yanni ChenDale E. HocevarPublished in: GLOBECOM (2003)
Keyphrases
- hardware implementation
- low density parity check
- hardware architecture
- ldpc codes
- xilinx virtex
- decoding algorithm
- rate allocation
- distributed video coding
- low complexity
- field programmable gate array
- signal processing
- error correction
- channel capacity
- low cost
- vlsi architecture
- distributed source coding
- high speed
- message passing