Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders.
Christoph RothAlessandro CevreroChristoph StuderYusuf LeblebiciAndreas BurgPublished in: ISCAS (2011)
Keyphrases
- energy efficiency
- vlsi implementation
- response time
- traffic load
- power consumption
- vlsi architecture
- energy consumption
- wireless sensor networks
- decoding algorithm
- energy efficient
- sensor networks
- data center
- high performance computing
- smart home
- power saving
- packet delivery
- low power
- energy saving
- routing protocol
- channel coding
- fir filters
- error correction
- associative memory
- filter bank
- quality of service
- neural network
- mac protocol
- sensor nodes
- artificial neural networks