Performance evaluation for a compressed-VLIW processor.

Sunghyun Jee Kannappan Palaniappan

Published in: SAC (2002)

Keyphrases

level parallelism
high speed
data structure
single chip
neural network
high end
parallel processing
data compression
compressed domain
multi core processors
industry standard
computer architecture
database systems
information systems
parallel architecture
parallel architectures
multiprocessor systems
real time