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A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation.
Mankoo Lee
Published in:
IEEE J. Solid State Circuits (1998)
Keyphrases
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power dissipation
high speed
power consumption
low power
chip design
cmos technology
digital signal processing
vlsi circuits
single chip
real time
power management
evaluation model
cost effective
model validation
design methodology
vlsi design
genetic algorithm
neural network