Speedy FPGA-based packet classifiers with low on-chip memory requirements.
Chih-Hsun ChouFong PongNian-Feng TzengPublished in: FPGA (2012)
Keyphrases
- memory requirements
- memory space
- decision trees
- memory usage
- computational speed
- test set
- computational complexity
- low memory
- low cost
- computational power
- high speed
- feature set
- training data
- machine learning
- classification algorithm
- training set
- packet loss
- linear classifiers
- machine learning algorithms
- svm classifier
- naive bayes
- low power consumption
- support vector
- content addressable memory
- class labels
- network devices
- hardware software
- single chip
- training samples
- feature vectors
- learning algorithm