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Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip.
Umesh Gajanan Nawathe
Mahmudul Hassan
King C. Yen
Ashok Kumar
Aparna Ramachandran
David Greenhill
Published in:
IEEE J. Solid State Circuits (2008)
Keyphrases
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cost effective
efficient implementation
vlsi implementation
highly optimized
database
low cost
low overhead
high speed
power consumption
circuit design
low power
complexity analysis
multithreading
cmos technology
ibm power processor