Network-on-chip for a partially reconfigurable FPGA system.
Justin A. HoganRaymond J. WeberBrock J. LaMeresTodd KaiserPublished in: ICS (2013)
Keyphrases
- distributed systems
- network on chip
- interconnection networks
- fault tolerant
- message passing
- field programmable gate array
- hardware implementation
- routing algorithm
- digital signal
- systolic array
- low cost
- network simulator
- multi processor
- reconfigurable hardware
- data transfer
- multistage
- embedded systems
- single chip
- hardware architecture
- signal processing
- hardware design
- software implementation
- image processing algorithms
- general purpose
- ad hoc networks
- efficient implementation
- web services
- parallel algorithm
- high speed
- wireless sensor networks
- power dissipation
- file system
- computing systems
- image processing