Using 3-valued memory representation for state space reduction in embedded assembly code model checking.
Thomas ReinbacherMartin HorauerBastian SchlichPublished in: DDECS (2009)
Keyphrases
- model checking
- space reduction
- temporal logic
- finite state machines
- transition systems
- temporal properties
- formal verification
- automated verification
- formal specification
- finite state
- model checker
- symbolic model checking
- verification method
- reachability analysis
- computation tree logic
- partial order reduction
- principal component analysis
- bounded model checking
- concurrent systems
- feature space
- timed automata
- epistemic logic
- deterministic finite automaton
- asynchronous circuits
- formal methods
- pspace complete
- artificial intelligence
- binary decision diagrams
- satisfiability problem
- image processing