A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC.
Sangyeop LeeKyoya TakanoShuhei AmakawaTakeshi YoshidaMinoru FujishimaPublished in: IEICE Trans. Electron. (2023)
Keyphrases
- power consumption
- clock gating
- silicon on insulator
- nm technology
- high speed
- low power
- cmos technology
- power reduction
- power management
- random sampling
- power dissipation
- clock frequency
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- power saving
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- ibm power processor
- sample size
- sampling strategy
- image sensor
- sampling methods
- monte carlo
- hd video
- infrared
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