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An Accurate Worst Case Timing Analysis for RISC Processors.
Sung-Soo Lim
Young Hyun Bae
Gyu Tae Jang
Byung-Do Rhee
Sang Lyul Min
Chang Yun Park
Heonshik Shin
Kunsoo Park
Soo-Mook Moon
Chong-Sang Kim
Published in:
IEEE Trans. Software Eng. (1995)
Keyphrases
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worst case
parallel algorithm
high accuracy
greedy algorithm
instruction set
highly accurate
computationally efficient
upper bound
parallel processing
average case
neural network
lower bound
application specific
parallel computing
parallel computation
high end
np hard
shared memory
high quality