A 3μW 500 kb/s ultra low power analog decoder with digital I/O in 65 nm CMOS.
Reza MerajiJohn B. AndersonHenrik SjölandViktor ÖwallPublished in: ICECS (2013)
Keyphrases
- ultra low power
- mixed signal
- low power
- cmos technology
- cmos image sensor
- circuit design
- low cost
- high speed
- power consumption
- analog vlsi
- knowledge base
- metal oxide semiconductor
- analog to digital converter
- nm technology
- successive approximation
- single chip
- input output
- dynamic range
- low complexity
- delta sigma
- digital signal processing
- multi channel
- solid state
- wide dynamic range
- data conversion
- low voltage
- image sensor
- silicon on insulator
- parallel processing
- processing capabilities