Performance Evaluation of SIMD Processor Architectures Using Pairwise Multiplier Recoding.
Todd C. MarekEdward W. DavisPublished in: ICPP (1) (1993)
Keyphrases
- single instruction multiple data
- pairwise
- parallel architectures
- parallel processing
- single processor
- highly parallel
- real time
- massively parallel
- similarity measure
- processing elements
- multicore processors
- high speed
- multi class
- pairwise interactions
- higher order
- parallel algorithm
- high end
- floating point
- loss function
- hardware implementation
- similarity function
- point sets
- spectral clustering
- multi core processors
- fine grained
- memory management
- high order
- parallel computers
- markov random field
- memory bandwidth
- general purpose
- efficient implementation
- parallel computing
- statistical significance
- low power
- neural network
- memory hierarchy
- belief propagation
- single chip
- interior point methods
- pairwise constraints
- graph matching