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Low latency low power bit flipping algorithms for LDPC decoding.

Mohamed IsmailImran AhmedJustin P. CoonSimon ArmourTaskin KoçakJoe McGeehan
Published in: PIMRC (2010)
Keyphrases
  • low power
  • decoding algorithm
  • low density parity check
  • ldpc codes
  • low latency
  • high speed
  • low cost
  • power consumption
  • digital signal processing
  • highly efficient
  • real time
  • operating system
  • vlsi architecture