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Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers.
Mahendra Rathor
Vishesh Mishra
Urbi Chatterjee
Published in:
DATE (2023)
Keyphrases
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floating point
hardware design
sparse matrices
multimedia
linear programming
fixed point
fpga hardware
artificial intelligence
data structure
parallel architectures
instruction set