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A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS.
Dongmin Park
SeongHwan Cho
Published in:
ISSCC (2012)
Keyphrases
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delta sigma
analog to digital converter
high speed
power consumption
noise shaping
clock frequency
low power
delta sigma modulators
cmos technology
power supply
hd video
image sensor
mixed signal
real time
cmos image sensor
image coding
high frequency