A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology.
Jitendra Kumar MishraHarshit SrivastavaPrasanna Kumar MisraManish GoswamiPublished in: iSES (2018)
Keyphrases
- low power
- power consumption
- cmos technology
- high speed
- low cost
- low power consumption
- nm technology
- power reduction
- power dissipation
- high power
- single chip
- wireless transmission
- vlsi architecture
- logic circuits
- digital signal processing
- vlsi circuits
- signal processor
- long range
- gate array
- low voltage
- image processing
- image sensor