A hierarchical N-Queen decimation lattice and hardware architecture for motion estimation.
Chung-Neng WangShin-Wei YangChi-Min LiuTi-Hao ChiangPublished in: IEEE Trans. Circuits Syst. Video Technol. (2004)
Keyphrases
- hardware architecture
- motion estimation
- block matching
- hardware implementation
- video coding
- hardware architectures
- motion compensated
- optical flow
- super resolution
- image sequences
- motion compensation
- motion vectors
- rate distortion
- video compression
- coarse to fine
- processing elements
- field programmable gate array
- xilinx virtex
- reference frame
- power consumption
- computer vision
- fine grained
- general purpose
- high level
- image processing