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Design of 12bit 100MHz Sample and Hold circuit for pipeline ADC.
Hao Zheng
Xiangning Fan
Yutao Sun
Published in:
WCSP (2011)
Keyphrases
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high speed
computer aided
evolvable hardware
real time
user interface
case study
building blocks
circuit design
evolutionary algorithm
design process
sample size
single chip
hardware architecture
analog to digital converter