A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS.
Srinivasan GopalPawan AgarwalJoe BaylonLuke RenaudSheikh Nijam AliPartha Pratim PandeDeukhyoun HeoPublished in: IEEE J. Emerg. Sel. Topics Circuits Syst. (2018)
Keyphrases
- spatial information
- nm technology
- low cost
- spatial and temporal
- spatial data
- high speed
- low power
- silicon on insulator
- power consumption
- spatio temporal
- user interface
- cmos technology
- spatial distribution
- spatial objects
- spatial databases
- space time
- minimum bounding rectangles
- random access memory
- interface design
- low rank
- frequency domain
- user friendly
- efficient computation
- linear algebra
- hardware implementation
- spatial relationships