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A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM.
Haonan Zhu
Bi Wu
Tianyang Yu
Ke Chen
Chenggang Yan
Weiqiang Liu
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2024)
Keyphrases
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random access memory
embedded dram
design considerations
memory requirements
high efficiency
data structure
memory space
high reliability
memory size
virtual memory
compute intensive