A Novel Power Reduction Technique for Block Matching Motion Estimation Hardware.
Abdulkadir AkinOnur Can UluselTevfik Zafer OzcanGokhan SayilarIlker HamzaogluPublished in: FPL (2011)
Keyphrases
- power reduction
- block matching motion estimation
- hardware architecture
- power consumption
- low power
- low cost
- efficient implementation
- multithreading
- power saving
- video coding
- real time
- hardware implementation
- high speed
- video compression
- pattern recognition
- digital signal processing
- motion estimation
- computational power
- field programmable gate array
- image sequences
- image processing