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A novel flip-flop based error free, area efficient and low power pipeline architecture for finite impulse recursive system.
Raja Krishnamoorthy
S. Saravanan
Published in:
Clust. Comput. (2019)
Keyphrases
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low power
error free
low cost
power consumption
high speed
power dissipation
pipeline architecture
cmos technology
real time
digital signal processing
efficient implementation
image processing
hardware implementation