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An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS.

Vito GianniniPierluigi NuzzoVincenzo ChironiAndrea BaschirottoGeert Van der PlasJan Craninckx
Published in: ISSCC (2008)
Keyphrases
  • noise tolerant
  • noisy data
  • analog to digital converter
  • circuit design
  • instance based learning algorithms
  • metal oxide semiconductor
  • power consumption
  • high speed
  • data sets
  • machine learning
  • statistical queries