Half-buffer retiming and token cages for synchronous elastic circuits.

Published in: IET Comput. Digit. Tech. (2011)

Keyphrases

analog circuits
analog vlsi
elastic matching
buffer size
asynchronous communication
delay insensitive
buffer allocation
circuit design
high level synthesis
database
vlsi circuits
electronic circuits
buffer management
steady state
database systems
neural network
data sets
real time