Reconfigurable hardware architecture of the spatial pooler for hierarchical temporal memory.
Abdullah M. ZyarahDhireesha KudithipudiPublished in: SoCC (2015)
Keyphrases
- reconfigurable hardware
- hierarchical temporal memory
- low cost
- hardware software
- hardware implementation
- functional units
- evolvable hardware
- image processing
- fine grain
- evolutionary algorithm
- field programmable gate array
- hardware design
- signal processing
- data flow
- processing elements
- massively parallel
- real time
- design methodology
- computer systems
- neural network