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Design and Analysis of High Performance and Low Power Matrix Filling for DNA Sequence Alignment Accelerator Using ASIC Design Flow.
N. Khairudin
M. A. Haron
S. A. M. Al Junid
A. K. Abdul Halim
M. F. M. Idros
N. F. Abdul Razak
Published in:
EMS (2011)
Keyphrases
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low power
low cost
high speed
design process
single chip
image processing
logic circuits
pairwise
statistically significant
power consumption
application specific
vlsi architecture