Login / Signup
Using Codes with Summation of Weighted Bits to Organize Checking of Combinational Logical Devices.
Dmitry V. Efanov
Valery V. Sapozhnikov
Vladimir V. Sapozhnikov
Published in:
Autom. Control. Comput. Sci. (2019)
Keyphrases
</>
error correcting codes
logical operations
parity check
block codes
mobile devices
reed solomon codes
error correction
error correcting
weighted sum
binary codes
electronic devices
logical reasoning
logical structure
asynchronous circuits
gray code