An RSA Encryption Hardware Algorithm using a Single DSP Block and a Single Block RAM on the FPGA.
Bo SongKensuke KawakamiKoji NakanoYasuaki ItoPublished in: Int. J. Netw. Comput. (2011)
Keyphrases
- hardware implementation
- block wise
- learning algorithm
- real time
- computational complexity
- low cost
- signal processing
- software implementation
- hardware architecture
- fractal encoding
- chaotic sequence
- block matching
- optimal solution
- hardware design
- image processing algorithms
- high speed
- fpga implementation
- k means
- systolic array