Login / Signup
FPGA Implementation of an Efficient High Speed Max-log-MAP Decoder.
Aishwarya Ambat
Karthi Balasubramanian
B. Yamuna
Deepak Mishra
Published in:
ICACCI (2018)
Keyphrases
</>
fpga implementation
high speed
hardware implementation
field programmable gate array
real time
machine learning
signal processing
frame rate
image processing algorithms
artificial intelligence
image analysis
control system
low power