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System-level PVT variation-aware power exploration of on-chip communication architectures.

Sudeep PasrichaYoung-Hwan ParkNikil D. DuttFadi J. Kurdahi
Published in: ACM Trans. Design Autom. Electr. Syst. (2009)
Keyphrases
  • higher level
  • low cost
  • power consumption
  • communication systems
  • levels of abstraction
  • multithreading
  • high speed
  • analog vlsi
  • chip design