Asic design of low power VLSI architecture for different multiplier algorithms using compressors.
R. AbhilashSanjay DubeyM. C. ChinnaiahPublished in: ICIIS (2016)
Keyphrases
- vlsi architecture
- low power
- single chip
- digital signal processing
- low cost
- power consumption
- high speed
- vlsi implementation
- low complexity
- logic circuits
- real time
- low power consumption
- mixed signal
- gate array
- power dissipation
- image processing algorithms
- hardware implementation
- cmos technology
- design methodology
- power reduction
- fir filters
- image sequences
- image processing
- computer vision