A low power high performance design for JPEG Huffman decoder.
Kun-Lin TsaiPaul LanShanq-Jang RuanMon-Chau ShiePublished in: ICECS (2008)
Keyphrases
- low power
- low power consumption
- low cost
- power consumption
- single chip
- high speed
- vlsi architecture
- logic circuits
- low density parity check
- digital signal processing
- power dissipation
- power reduction
- image compression
- gate array
- ultra low power
- real time
- cmos technology
- fpga implementation
- decoding algorithm
- coding method
- transform domain
- image coding
- ldpc codes
- mixed signal