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Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures.

Pedro Tauã Lopes PereiraGuilherme PaimGuilherme FerreiraEduardo A. C. da CostaSérgio AlmeidaSergio Bampi
Published in: LASCAS (2021)
Keyphrases
  • hardware architectures
  • computational power
  • computationally efficient
  • frequency domain
  • cost effective
  • neural network
  • pattern recognition
  • data processing
  • single phase