Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes.
Marzieh Hashemipour-NazariKees GoossensAlexios Balatsoukas-StimmingPublished in: ICASSP (2021)
Keyphrases
- hardware implementation
- decoding algorithm
- error control
- signal processing
- efficient implementation
- low density parity check
- ldpc codes
- hardware architecture
- joint source channel
- error correcting
- error correction
- fpga implementation
- parity check
- reed solomon
- hardware design
- software implementation
- dedicated hardware
- machine learning
- fractal encoding
- real time
- memory management
- pattern recognition
- image binarization
- fpga device
- field programmable gate array
- turbo codes
- parallel architecture
- software engineering
- coding scheme
- pipeline architecture
- pipelined architecture
- image transmission
- reed solomon codes