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Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.
Yu Wang
Ku He
Rong Luo
Hui Wang
Huazhong Yang
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2008)
Keyphrases
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fine grain
coarse grain
high speed
parallel computation
power dissipation
distributed memory
circuit design
low power
real time
integrated circuit
low cost
nested transactions
power consumption
parallel algorithm
response time
management system
databases