Login / Signup
Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip.
Akash Kumar
Andreas Hansson
Jos Huisken
Henk Corporaal
Published in:
DATE (2007)
Keyphrases
</>
low cost
single chip
multi processor
reconfigurable hardware
high speed
hardware software
embedded systems
systolic array
hardware implementation
multi core processors
low power consumption
computer systems
power reduction
distributed systems
low power
field programmable gate array
general purpose
network on chip