Login / Signup
A low-power IP design of Viterbi decoder with dynamic threshold setting.
Yi-Ming Lin
Wan-Ching Liu
Li-Yuan Chang
Chih-Yuan Lien
Pei-Yin Chen
Shung-Chih Chen
Published in:
ISCAS (2010)
Keyphrases
</>
low power
single chip
power consumption
vlsi architecture
logic circuits
low cost
high speed
low power consumption
digital signal processing
cmos technology
power dissipation
power reduction
gate array
design process
hidden markov models
mixed signal
high power
image compression
nm technology