Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology.

Feng Ge P. Jain Ken Choi

Published in: EIT (2009)

Keyphrases

low power
cmos technology
ultra low power
high speed
low cost
single chip
power consumption
low power consumption
digital signal processing
low voltage
power dissipation
mixed signal
spl times
image sensor
real time
embedded systems
computer architecture
circuit design
efficient implementation
design methodology
parallel processing