A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing.
Shaolei QuanQiang QiangChin-Long WeyPublished in: ISCAS (4) (2005)
Keyphrases
- digital signal processing
- low power
- reconfigurable architecture
- high speed
- power consumption
- low cost
- systolic array
- single chip
- hardware implementation
- floating point
- vlsi circuits
- logic circuits
- vlsi architecture
- data flow
- low power consumption
- mixed signal
- gate array
- cmos technology
- image sensor
- fine grained
- higher order
- nm technology