3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans.

Vitor de Paulo Cristinel Ababei

Published in: Int. J. Reconfigurable Comput. (2010)

Keyphrases

network on chip
routing algorithm
interconnection networks
multi processor
network simulator
packet switched
parallel algorithm
data transfer
multi core processors
wireless sensor networks
multistage
fault tolerant