Systolic array implementations of neural nets on the MasPar MP-1 massively parallel processor.
G. ChinnK. A. GrajskiC. ChenC. KuszmaulS. TomboulianPublished in: IJCNN (1990)
Keyphrases
- massively parallel
- systolic array
- neural nets
- reconfigurable architecture
- parallel architecture
- data flow
- feed forward
- fine grained
- back propagation
- parallel computing
- artificial neural networks
- neural network
- high performance computing
- parallel architectures
- parallel computers
- learning tasks
- parallel machines
- processing elements
- hardware implementation
- parallel programming
- efficient implementation
- parallel processing
- decision trees
- blue gene
- markov random field
- graph cuts