A high-performance area-aware DSP processor architecture for video codecs.

Lan-Da Van Hsin-Fu Luo Chien-Ming Wu Wen-Hsiang Hu Chun-Ming Huang Wei-Chang Tsai

Published in: ICME (2004)

Keyphrases

video codec
systolic array
parallel architecture
video coding
computation intensive
high speed
video decoder
image and video coding
rate distortion
real time
signal processing
motion compensation
distributed memory
video quality
motion compensated
embedded dram
transform domain
multiscale
motion vectors
high quality