High speed algorithm and VLSI architecture design for decoding BCH product codes.
Zhipei ChiKeshab K. ParhiPublished in: ICASSP (2002)
Keyphrases
- high speed
- times faster
- computational complexity
- detection algorithm
- optimal solution
- worst case
- learning algorithm
- dynamic programming
- experimental evaluation
- convergence rate
- matching algorithm
- cost function
- vlsi architecture
- vlsi implementation
- preprocessing
- optimization algorithm
- search space
- computational cost
- k means
- image quality
- signal processing
- simulated annealing
- recognition algorithm
- np hard