Understanding the Insecurity of Processor Caches Due to Cache Timing-Based Vulnerabilities.

Shuwen Deng Wenjie Xiong Jakub Szefer

Published in: IEEE Secur. Priv. (2021)

Keyphrases

memory access
cache misses
caching scheme
high speed
cache hit ratio
information security
embedded processors
processor core
main memory
data access
prefetching
multithreading
access latency
shared memory
memory subsystem
shared memory multiprocessors