Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug.

Yousef Iskander Cameron D. Patterson Stephen D. Craven

Published in: FPL (2011)

Keyphrases

trade off
fpga implementation
user interface
engineering design
signal processing
real time
design process
knowledge based systems
verilog hdl
single chip
design principles
design patterns
building blocks
high speed
low cost
case study
image processing
e learning