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A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme.

Kyomin SohnTaesik NaIndal SongYong ShimWonil BaeSanghee KangDongsu LeeHangyun JungSeok-Hun HyunHanki JeoungKi Won LeeJun-Seok ParkJongeun LeeByunghyun LeeInwoo JunJuseop ParkJunghwan ParkHundai ChoiSanghee KimHaeyoung ChungYoung ChoiDae-Hee JungByungchul KimJung-Hwan ChoiSeong-Jin JangChi-Wook KimJung-Bae LeeJoo-Sun Choi
Published in: IEEE J. Solid State Circuits (2013)
Keyphrases
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