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An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS.
Kevin Zheng
Yohan Frans
Sai Lalith Ambatipudi
Santiago Asuncion
Hari Teja Reddy
Ken Chang
Boris Murmann
Published in:
VLSI Circuits (2018)
Keyphrases
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back end
analog vlsi
high speed
wireless networks
data conversion
control algorithm
analog circuits
circuit design
induction motor
digital computer
frequency response
building blocks
focal plane
fuzzy controller
long range
single phase
user friendly
data management