RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions.

Takuto Kanamori Kenji Kise

Published in: MCSoC (2021)

Keyphrases

instruction set
instruction set architecture
processor core
data structure
parallel processing
application specific
computation intensive
integrated circuit
computer architecture
high speed
decision support
floating point
database systems
compression ratio
data compression
hardware architecture