Design of a low power, high speed self calibrated dynamic latched comparator.
Sumit Kumar JaiswalAnnapurna MondalSupriyo SrimaniSubhajit DasKasturi GhoshHafizur RahamanPublished in: ISDCS (2020)
Keyphrases
- low power
- high speed
- single chip
- low cost
- low power consumption
- power consumption
- vlsi architecture
- logic circuits
- digital signal processing
- gate array
- mixed signal
- cmos technology
- power dissipation
- high power
- wireless transmission
- power reduction
- frame rate
- ultra low power
- real time
- image sensor
- error correction
- vlsi circuits
- nm technology
- parallel processing