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POSET timing and its application to the synthesis and verification of gate-level timed circuits.

Chris J. MyersTomas RokickiTeresa H.-Y. Meng
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1999)
Keyphrases
  • asynchronous circuits
  • petri net
  • high speed
  • texture synthesis
  • analog circuits
  • formal verification
  • delay insensitive
  • logic synthesis
  • discrete event
  • cmos technology
  • analog vlsi